| 1. |
- Cui, L., et al.
(författare)
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A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash
- 2022
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Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 0278-0070 .- 1937-4151. ; 41:6, s. 1971-1975
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Tidskriftsartikel (refereegranskat)abstract
- For NAND flash memory, designing a good low-density parity-check (LDPC) decoding algorithm could ensure data reliability. When the decoding algorithm is implemented in hardware, it is necessary to achieve attractive trade off between implementation complexity and decoding performance. In this paper, a novel low bit-width decoding scheme is introduced. In this scheme, the Quasi-Cyclic LDPC (QC-LDPC) is used, and the row-layered normalized min-sum algorithm is improved by restricting the amplitude of minimum and second-minimum values in each check node (CN) updating. The simulation shows that our approach achieves a lower UBER (Uncorrectable Bit Error Rate) with a negligible increase in computational complexity, especially with low precision input log-likelihood ratio (LLR).
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| 2. |
- Liu, W, et al.
(författare)
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DEPS : Exploiting a Dynamic Error Prechecking Scheme to Improve the Read Performance of SSD
- 2021
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Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - : Institute of Electrical and Electronics Engineers Inc.. - 0278-0070 .- 1937-4151. ; 40:1, s. 66-77
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Tidskriftsartikel (refereegranskat)abstract
- 3D NAND flash memory is gradually being widely used in solid state drives (SSD), leading to increasing storage capacity. However, the read performance of SSD is sacrificed for decoding operations which are executed to guarantee the data reliability. No matter whether the data have bit errors, they will be sent to error correcting code (ECC) engine to decode, introducing a high read delay of SSD. Error prechecking can help to avoid the redundant decoding operations for the error-free data, but it induces extra checking overhead to the error data. Motivated by this, we carry out comprehensive experiments to analyze the distribution of bit errors in 3D NAND flash memory. The preliminary experimental results show that there are a large number of pages read without errors in the early lifetime of 3D NAND flash memory. Based on the observations and analyses, we propose a model to estimate the error-free ratio, and utilize it to design a dynamic error prechecking scheme (DEPS) to bypass the decoding operation for the error-free data in 3D NAND flash memory and improve the read performance of SSD. Furthermore, by dividing a large page into small subpages, DEPS releases more error-free data, which significantly improves the read performance of SSD. Evaluation results from real-world traces demonstrate that by implementing DEPS, the average read performance of SSD is enhanced by 35% 55% with 3D MLC NAND flash memory.
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| 3. |
- Wang, S., et al.
(författare)
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Lifetime adaptive ECC in NAND flash page management
- 2017
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Ingår i: Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017. - : Institute of Electrical and Electronics Engineers (IEEE). - 9783981537093 ; , s. 1253-1256
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Konferensbidrag (refereegranskat)abstract
- NAND flash memory has decreasing storage reliability, as the density or program/erase (P/E) cycle increases. To ensure data integrity, error correction codes (ECCs) are widely employed and typically stored in the out-of-band area (OOB) of flash pages. However, the worst-case oriented ECC is largely under-utilized in the early stage (small P/E cycles), and the required ECC redundancy may be too large to fit in OOB in the late stage (high P/E cycles). In this paper, we propose LAE-FTL, which employs a lifetime-adaptive ECC scheme, to improve the performance and lifetime of NAND flash memory. LAE-FTL uses weak ECCs in the early stage and strong ECCs in the late stage to guarantee the storage reliability. Since OOB is large enough to store weak ECCs in the early stage, small and size-incremental codewords are adaptively used to improve data transfer and decoding parallelism. In the late stage, strong ECCs have to be employed and the ECC redundancies become too large to be stored in OOB. Thus, LAE-FTL stores the exceeding ECC redundancies in the data space of flash pages and stores user data in a cross-page fashion. Finally, our trace-driven simulation results show that LAE-FTL improves the read performance by up to 63.42%, compared to the worst-case oriented ECC scheme in the early stage, and significantly improve the storage reliability at low cost in the late stage.
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| 4. |
- Wang, S., et al.
(författare)
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WARD : Wear aware RAID design within SSDs
- 2018
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Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - : Institute of Electrical and Electronics Engineers Inc.. - 0278-0070 .- 1937-4151. ; 37:11, s. 2918-2928
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Tidskriftsartikel (refereegranskat)abstract
- Redundant arrays of independent disk (RAID) is an efficient approach to relieve reliability sacrifice caused by aggressive scale-out of solid state drives (SSDs). Unfortunately, RAID is unfriendly to SSDs due to redundant parity write and data rebuilding. This paper proposes a wear aware RAID design for SSDs, called WARD, which: 1) adaptively organizes RAID stripes according to real-time interblock unbalanced wear for relieving high performance and storage overhead caused by parity data and 2) migrates blocks about to break in advance and leaves these blocks unused to reduce data rebuilding overhead. An efficient block wear detection scheme is employed to detect block wear during the whole lifetime of SSDs. Beginning with a large stripe width RAID instead of the redundant worst-case RAID, WARD reorganizes RAID stripes once wear blocks with high bit error rates come out. WARD divides the original stripe into several short width RAID stripes according to the number of wear blocks and separates all wear blocks into different stripes. This not only reduces parity redundancy but also provides high reliability to avoid more than RAID recoverable error-prone chunks remaining in one stripe. For high wear blocks tending to wear-out, data in them are migrated in advance and then the blocks are left unused, which efficiently avoids performance shock caused by data rebuilding. A reliability model considering interblock unbalanced wear is proposed and reveals that WARD provides a high and stable reliability and greatly prolongs the lifetime of SSDs. Comprehensive experiments based on an SSDsim derivative simulator are carried out and experiment results show that WARD considerably improves system performance compared to the worst-case RAID.
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| 5. |
- Xiong, Q., et al.
(författare)
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Characterizing 3D floating gate NAND flash
- 2017
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Ingår i: SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems. - New York, NY, USA : Association for Computing Machinery (ACM). - 9781450350327 ; , s. 31-32
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Konferensbidrag (refereegranskat)abstract
- In this paper, we characterize a state-of-The-Art 3D oating gate NAND ash memory through comprehensive experiments on an FPGA platform. Then, we present distinct observations on performance and reliability, such as operation latencies and various error patterns. We believe that through our work, novel 3D NAND ash-oriented designs can be developed to achieve better performance and reliability.
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| 6. |
- Xiong, Q., et al.
(författare)
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Extending Real-Time Analysis for Wormhole NoCs
- 2017
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Ingår i: IEEE Transactions on Computers. - : IEEE Computer Society. - 0018-9340 .- 1557-9956. ; 66:9, s. 1532-1546
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Tidskriftsartikel (refereegranskat)abstract
- The delay upper-bound analysis problem is of fundamental importance to real-Time applications in Network-on-Chips (NoCs). In the paper, we revisit two state-of-The-Art analysis models for real-Time communication in wormhole NoCs with priority-based preemptive arbitration and show that the models only support specific router architectures with large buffer sizes. We then propose an extended analysis model to estimate delay upper-bounds for all router architectures and buffer sizes by identifying and analyzing the differences between upstream and downstream indirect interferences according to the relative positions of traffic flows and taking the buffer influence into consideration. Simulated evaluations show that our model supports one more router architecture and applies to small buffer sizes compared to the previous models.
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| 7. |
- Xiong, Q., et al.
(författare)
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Real-time analysis for wormhole NoC : Revisited and revised
- 2016
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Ingår i: Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. - New York, NY, USA : Association for Computing Machinery (ACM). - 9781450342742 ; , s. 75-80
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Konferensbidrag (refereegranskat)abstract
- The network delay upper-bound analysis problem is of fundamental importance to real-time applications in Network-on-Chip (NoC). In the paper, we revisit a state-of-the-art analysis model for real-time communication in wormhole NoC with priority-based preemptive arbitration and show that the model may provide pessimistic or even incorrect network delay upper-bound. We then propose a revised analysis model to correct the flaws in the previous model by further classifying indirect interference as upstream and downstream indirect interferences according to the relative positions of traffic flows and taking buffer influence into consideration. Simulated evaluations show that our model provides tighter and correct network delay upper-bound compared with the state-of-the-art model.
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| 8. |
- Zhu, Y., et al.
(författare)
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ALARM : A Location-Aware Redistribution Method to Improve 3D FG NAND Flash Reliability
- 2017
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Ingår i: 2017 IEEE International Conference on Networking, Architecture, and Storage, NAS 2017 - Proceedings. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781538634868
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Konferensbidrag (refereegranskat)abstract
- 3D NAND flash memory is enjoying an increasing popularity as it dramatically increases the bit density, presenting a grand opportunity to satisfy the growing demand on the storage capacity. However, this vertically stacked structure also introduces more serious read disturb problems compared with planar flash devices. Characterization results show that the read disturb errors on 3D floating gate (FG) MLC NAND flash chips exhibit a large discrepancy on the locations and types of pages, implying that pages should not be treated equally when designing migration schemes. This paper makes a thorough observation on read access characteristics by analyzing contemporary workloads collected from a wide range of applications with various read ratios. Based on the characterization results, we build a read disturb error model and propose a location-aware redistribution method (ALARM) that utilizes the intrinsic characteristics of the 3D floating gate NAND flash and redistributes read-hot pages to locations inducing less read disturb errors to improve its reliability. We implement the read disturb error model and our proposed design on an event-driven simulator, and the experimental results show that ALARM can reduce the maximum and average raw bit error rates (RBERs) by up to 99.49% and 91.80% with an operation overhead of 0.70%.
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